A delay adjustment circuit includes a first gate group in which each gate is coupled in series to carry out fine adjustment of a delay time of an input signal, a load capacity that is coupled to an output side of a particular gate out of the first gate group via a first switch mechanism, and a second gate group that is coupled to an output side of the first gate group via a second switch mechanism to carry out coarse adjustment of a delay time of an input signal. The first and second switch mechanisms are controlled, by adjusting the load capacity that is coupled to the output side of the particular gate out of the first gate group and a number of gate stages of the second gate group, so as to adjust the delay time of the input signal.
One of such related techniques is disclosed in Japanese Laid-open Patent Publication No. 2001-217694.